1. Field of the Invention
The present invention relates to a circuit board for mounting a bare chip in the form of a flip chip.
The present application is based on Japanese Patent Application No. Hei. 10-176422, which is incorporated herein by reference.
2. Description of the Related Art
With an development of downsizing or high-performance of an electronic appliance in recent years, a semiconductor device constituting the electronic appliance and a multi-layer printed wiring board for mounting or packaging it have been demanded to realize downsizing/low-profiling, high performance and high reliability. In order to satisfy such a demand, the type of a package has been shifted from a pin-insertion type package to surface-mounting package. Recently, a flip-chip packaging technique has been developed which directly mounts a bare semiconductor element (bare chip) not packaged on a printed wiring board.
On the other hand, in flip-chip mounting, a Si chip having a thermal expansion coefficient of 3-4 ppm/xc2x0 C. is directly bonded onto a printed wiring board having a thermal expansion coefficient of 10-20 ppm/xc2x0 C. through an adhesive. Therefore, stress is generated at a connecting portion owing to a difference in the thermal expansion coefficient therebetween. This reduces reliability of connection. Specifically, owing to the stress due to the difference in the thermal expansion coefficient, cracks arise in the adhesive to lower humidity resistance and break the connecting portion. Then, in order to relax such stress, attempts for optimizing various properties of the adhesive to diffuse the stress have been made.
However, the above technique cannot realize sufficient reliability of connection. If higher-density connection is required and an increased size of the silicon chip is expected in the future, the problem of stress produced owing to a difference in the thermal expansion coefficient between the silicon chip and the printed wiring board will be more serious.
Meanwhile, in the mounting process, after the silicon chip and printed wiring board are bonded to each other, a thermosetting under-fill material is poured in therebetween to seal the Si chip. The Si chip thus mounted is removed, and another good Si chip is mounted again (repairing step). In the repairing step, if the interlayer bonding force is low in the printed wiring board, the circuit was cut halfway, and peeling-off occurred between the adjacent layers.
An object of the present invention is to provide a circuit board for mounting a bare chip which can improve a repairability of the bare chip and reliability of connection therebetween.
In order to attain the above object, the circuit board for mounting a bare chip according to the present invention is structured as a circuit board for mounting a bare chip in the form of a flip chip, wherein a metallic foil for protecting a circuit in a state insulated therefrom is arranged in an area where the bare chip is located.
As a result of eager investigation for improving the repairability and connection reliability between a circuit board and a bare chip mounted thereon in the form of a flip chip, the inventors of the present invention have found that if a metallic foil for protecting circuits in a state insulated therefrom is arranged in an area where the bare chip is located, it protects the circuit on the circuit board so that the circuit is not cut halfway or damaged when the bare chip mounted once is repaired and peeling-off does not occur between adjacent layers when the circuit board includes plural layers. In addition, as described later, the inventors have found that use of the metallic foil having a low thermal expansion property (close to that of a silicon chip) can relax a difference in the thermal expansion coefficient between the bare chip and circuit board and minimize the stress occurring in a solder connection portion to implement the flip-chip mounting with a high degree of reliability.
In the present invention, where through-holes are formed at predetermined positions of the metallic foil and the inner periphery of each of the through-holes is covered with an insulating material, these through-holes can be used as a space for electrically connecting the bare chip to be mounted to the circuits located below the metallic foil (which is used to insert an electrode provided on the bare chip at the time of mounting or previously provide the electrode on the circuit board).
In the present invention, where each of the through-holes is filled with a conductive material for connecting the bare chip to be mounted to the circuits located below the metallic foil, the though-hole can be used to provide the electrodes of a conductive material on the circuit board.
In the present invention, if the conductive material is solder, the electrodes made of solder can be easily provided in the though-holes.
In the present invention, if the metallic foil has a low thermal expansion coefficient of 10 ppm/xc2x0 C. or lower at 20-250xc2x0 C., such a metallic foil permits a difference in the thermal expansion coefficient between the bare chip and the circuit board to be relaxed and minimizes stress to be produced in an electrically connecting portion, the flip-chip mounting can be implemented with a high degree of reliability.
In the present invention, where the metallic foil is made of an Fe/Ni alloy containing Ni of 31-50 weight % and having a thickness of 10-100 xcexcm, this metallic foil can suppress a difference in the thermal expansion coefficient between the bare chip and the circuit board, thus providing excellent reliability of connection.
In the present invention, where the metallic foil is located in the area wider than the range where the pads of the bare chip to be mounted are formed, the metallic foil can surely give the effects of protecting the circuits on the circuit board and suppressing a difference in the thermal expansion coefficient between the bare chip and the circuit board.
Features and advantages of the invention will be evident from the following detailed description of the preferred embodiments described in conjunction with the attached drawings.